AN103 siliconix 10-mar-97 1 the fet constant-current source/limiter introduction the combination of low associated operating voltage and high output impedance makes the fet attractive as a constant-current source. an adjustable-current source (fig- ure 1) may be built with a fet, a variable resistor, and a small battery. for optimum thermal stability, the fet should be biased near the zero temperature coefficient point. d s + figure 1. field-effect transistor current source r s r l no tag whenever the fet is operated in the current saturated re- gion, its output conductance is very low. this occurs whenever the drain-source voltage v ds is at least 50% greater than the cut-off voltage v gs(off) . the fet may be biased to operate as a constant-current source at any cur- rent below its saturation current i dss . basic source biasing for a given device where i dss and v gs(off) are known, the approximate v gs required for a given i d is (1) v gs v gs(off) 1 i d i dss 1 k where k can vary from 1.8 to 2.0, depending on device ge- ometry. if k = 2.0, the series resistor r s required between source and gate is (2) r s v gs i d or r s v gs(off) i d 1 i d i dss a change in supply voltage or a change in load imped- ance, will change i d by only a small factor because of the low output conductance g oss . i d = ( v ds )(g oss ) (3) the value of g oss is an important consideration in the ac- curacy of a constant-current source where the supply volt- age may vary. as g oss may range from less than 1 s to more than 50 s according to the fet type, the dynamic impedance can be greater than 1 m to less than 20 k . this corresponds to a current stability range of 1 a to 50 a per volt. the value of g oss also depends on the op- erating point. output conductance g oss decrease approxi- mately linearly with i d . the relationship is (4) i d i dss g oss g oss where g oss = g oss (5) when v gs = 0 (6) so as v gs v gs(off) , g oss zero. for best regulation, i d must be considerably less than i dss . cascading for low g oss it is possible to achieve much lower g oss per unit i d by cascading two fets, as shown in figure 2. d s + sd figure 2. cascade fet current source v dd r s r l q 2 q 1 updates to this app note may be obtained via facsimile by calling siliconix faxback, 1-408-970-5600. please request faxback do cument #70596.
AN103 2 siliconix 10-mar-97 d s d s + + + (a) (b) figure 3. cascade fet v gs1 = 0 q 2 q 1 v gs2 g fs2 g oss2 i 2 v ds2 g oss1 v ds1 = v gs2 = i o /g oss1 i o v o now, i d is regulated by q 1 and v ds1 = v gs2 . the dc val- ue of i d is controlled by r s and q 1 . however, q 1 and q 2 both affect current stability. the circuit output conduc- tance is derived as follows: if g oss1 = g oss2 (7) (8) g o g oss 2 g fs g oss when rs 0 as in figure 2 (9) g o g oss 2 g fs 1 r s g fs in either case (r s = 0 or r s 0), the circuit output conductance is considerably lower than the g oss of a single fet. in designing any cascaded fet current source, both fets must be operated with adequate drain-gate voltage, v dg . that is, v dg v gs(off) , preferably v dg 2v gs(off) (10) if v dg < 2 v gs(off) , the g oss will be significantly increased, and circuit g o will deteriorate. for example: a jfet may have a typical g oss = 4 s at v ds = 20 v and v gs = 0. at v ds v gs(off) = 2 v, g oss 100 s. the best fets for current sources are those having long gates and consequently very low g oss . the siliconix 2n4340, j202, and sst202 exhibit typical g oss = 2 s at v ds = 20 v. these devices in the circuit of figure 4 will provide a current source adjustable from 5 a to 0.8 ma with internal impedance greater than 2 m at 0.2 ma. other siliconix part types such as the 2n4392, j112, and sst112 can provide 10 ma or higher current. q 1 d s + 30 v figure 4. adjustable current source r s = 1 m r s = 1 m r s 200 (optional) instead of the adjustable resistor, the jfets can be put in i dss range groupings with an appropriate r s resistor selected for each group. this method is common in high volume applications. the cascade circuit of figure 5 provides a current adjustable from 2 a to 0.8 ma with internal resistance greater than 10 m d s + 30 v d s q 2 q 1 100 (optional) r s q 1 = 2n4340, j202, sst202 q 2 = 2n4341, j304, sst304 r s = 1 m figure 5. cascade fet current source
AN103 siliconix 10-mar-97 3 cr470 cr430 cr390 cr360 cr330 cr300 cr270 cr240 cr220 cr200 cr180 cr160 sst/j504 sst/j503 sst/j502 j501 j500 part type 0.1 0.2 0.5 1 2 5 10 i f regulator current (ma) figure 6. standard series current regulator range to-18 2-lead package j = to-226aa 2-lead package sst = to-236 (sot-23) package i f v f sst/j510 sst/j509 sst/j508 sst/j507 sst/j506 sst/j505 sst/j511 standard two-leaded devices siliconix offers a special series of two-leaded jfets with a resistor fabricated on the device, thus creating a 10% current range. devices are available in ranges from 1.6 ma (cr160) to 4.7 ma (cr470). for designs requiring a 20% current range, siliconix offers devices rated from 0.24 ma typical (j500) through 4.7 ma typical (j511) in a two-leaded to-226a (to-92) package. the sst502 series is available in surface mount to-236 (sot-23). each of these two-leaded devices can be used to replace several typical components. figure 6 shows the current ranges of these two device series. further information is contained in the individual data sheets appearing elsewhere in this data book or from siliconix faxback. the cr160 series features guaranteed peak operating voltage minimum of 100 v with a typical of 180 v. the j500 series features 50 v minimum with a typical of 100 v. the lower current devices in both series provide excellent current regulation down to as little as 1 v. bias resistor selection all industry jfet part types exhibit a significant varia- tion in i dss and v gs(off) on min/max specifications and device-to-device variations. using the simple source biasing current source as illus- trated in figure 1, the designer can graphically calculate the r s which best fits the desired drain current i d. figure 7 plotting i d versus v gs over the military temperature range shows the resulting i d for different values of r s . the r s lines are constructed by drawing the slope of the r s desired value starting at the origin, eg. r s = 2 k slope. find a convenient point on the x y axis to mark a v gs i d of 2 k such as v gs = 1.5 v and i d = 0.75 ma. then, draw a straight line from this point to the origin. the intersection of this r s line and the device i d versus v gs will be the operating i d . in this example, the result- ing i d = 0.35 ma at t j = 25 c. the intercepts of the t j = 55 c and 125 c show the minimal variation with temperature. also note that jfets have a i d current where there is no change with temperature variation. to achieve this t c , the v gs voltage (i d x r s ) is approximately: v gs(0tc) v gs(off) 0.65 v (11)
AN103 4 siliconix 10-mar-97 figure 7. jfet typical transfer characteristic 2.00 0 1.2 1.6 2 0.8 0.4 0.25 0 v gs gate-source voltage (v) drain current (ma) i d v ds = 4 to 20 v 2n4339 max sst/j202 (low end) 0.50 0.75 1.00 1.25 1.50 1.75 t j = 55 c 125 c r s = 0.2 k 0.5 k 1 k 2 k 5 k 10 k 20 k 25 c figure 8. source biased drain-current vs. source resistance 1000 0.1 100 10 r s source resistance (k ) drain current ( i d a) v dd = 5 to 30 v t j = 25 c except as noted 10 1 100 t j = 55 c 125 c 2n/pn4119a sst4119 max 2n/pn4118a sst4118 max 2n/pn4119a sst4119 min 2n/pn4118a sst4118 min 2n/pn4117a sst4117 min 2n/pn4117a sst4117 max 0.5 50 5 figure 9. jfet source biased drain-current vs. source resistance 2 0.1 20 1 0.01 r s source resistance (k ) drain current (ma) i d 1 v dd = 4 to 20 v t j = 25 c except as noted r s 0.1 10 t j = 55 c 125 c sst/j202 max 2n4338 max sst/j202 min 2n4339 min sst/j201 max sst/j201 2n4338 min v dd 0.5 5 25 c 2n4339 max 25 c
AN103 siliconix 10-mar-97 5 choosing the correct jfet for source biasing each of the siliconix device data sheets include typical transfer curves that can be used as illustrated in figure 7. several popular devices are ideal for source biased cur- rent sources covering a few as to 20 ma. to aid the de- signer, the devices in table 1 have been plotted to show the drain current, i d , versus the source resistance, r s , in figures 8, 9, and 10. most plots include the likely worst case i d variations for a particular r s . for tighter current control, the jfet production lot can be divided into ranges with an appropriate resistor selection for each range. table 1: source biasing device recommendations practical current range i d (ma) through-hole plastic device surface mount device metal can device 0.01 0.02 pn4117a sst4117 2n4117a 0.01 0.04 pn4118a sst4118 2n4118a 0.02 0.1 pn4119a sst4119 2n4119a 0.01 0.1 j201 sst201 2n4338 0.02 0.3 j202 sst202 2n4339 0.1 2 j113 sst113 2n4393 0.2 10 j112 sst112 2n4392 55 c 20 0.1 10 0.1 r s source resistance (k ) drain current ( i d a) m 1 1 figure 10. jfet source biased drain-current vs. source resistance 10 r s v dd = 5 to 30 v t j = 25 c except as noted 125 c 2n4393, sst/j113 max mid 2n4392, sst/j112 min 2n4392, sst/j112 min 2n4393 sst/j113 mid v dd 5 0.5 t j = 25 c
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